SE3: Sequential Equivalence Checking for Non-Cycle-Accurate Design Transformations †
Published in 60th ACM/IEEE Design Automation Conference (DAC), 2023
Recommended citation: Y. Li, G. Zhao, Y. He and H. Zhou, "SE3: Sequential Equivalence Checking for Non-Cycle-Accurate Design Transformations †," 2023 60th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2023, pp. 1-6, doi: 10.1109/DAC56929.2023.10247912.
In high-level design explorations, many useful optimizations transform a circuit into another with different operating cycles for a better trade-off between performance and resource usage. How to efficiently check their equivalence is critical and challenging since most existing equivalence checkers are designed for cycle-accurate circuits. This paper presents SE3, an efficient sequential equivalence checker without assumption on cycle-accuracy, latch mapping, or I/O interface of the checked circuits. It proves the equivalence of two circuits by computing an equivalence relation between the states of the two circuits and utilizes syntax abstraction to accelerate this process. Experimental results show that SE3 is significantly faster than state-of-the-art sequential equivalence checking algorithms.