Ph.D. Candidate · Northwestern University
Yunqi He
Physical-design methodology & ML-driven automation for SoC PPA.
I build quality-preserving legalization, GPU-accelerated placement, and GNN- and agent-driven engines that drive the full floorplan-to-route flow — turning research primitives into reliable, production-grade design automation.
Research
Improving SoC PPA across placement, legalization, timing, and routing — and composing reliable engines into an agentic design flow.
Physical Design & Legalization
A TwinTree quality-preserving legalizer and GPU-accelerated placement that turn continuous placements into legal, high-quality layouts at industrial scale.
Learn more →ML for Physical Design
Graph neural networks for timing-driven placement initialization, routing-congestion prediction, and data-driven floorplanning.
Learn more →Agentic Design Automation
An LLM-driven agent that plans and executes the full floorplan-to-route flow under unified PPA objectives, staying on physically valid states.
Learn more →ICCAD · DAC · DATE · AAAI · TODAES
Recent news
- Jul 2026. Our paper **Quality-Preserving Legalization for Analytical Floorplanning** was accepted to **ICCAD 2026** (to appear).
- Jun 2026. Returned to **Cadence Design Systems** as an R&D intern, building GNN-based routing congestion prediction for the Palladium (Z4) emulator.
- Apr 2026. Our journal paper **Graph Neural Network based Initialization for Timing Driven Placement** appeared in **ACM TODAES**.
- Jan 2026. Awarded the **Northwestern University Terminal Year Fellowship** (2026).
- Nov 2025. Our paper **Physical-Aware eFPGA Redaction for Secure and Efficient Hardware IP Protection** was accepted to **DATE 2026**.
- Sep 2025. Submitted a paper on eFPGA-based hardware IP protection techniques to DATE 2026.
Let’s build better silicon.
I’m looking for full-time roles in physical design, design automation, and ML-for-EDA.