Research Projects
My research builds physical-design methodology and ML-driven automation to improve SoC PPA (power, performance, area) across placement, legalization, timing, and routing. I emphasize robust, reliable design flows — and apply data science and machine learning where it moves power, performance, and area — culminating in an agentic system that drives the full physical-design flow.
Quality-Preserving Legalization & GPU-Accelerated Placement
Core focus: turning continuous analytical placements into legal, physically valid layouts without sacrificing wirelength, area, or timing — at industrial scale.
- TwinTree legalizer: quality-preserving legalization with built-in topological invariants and a TAG graph abstraction ICCAD 2026
- GPU-accelerated placement: DREAMPlace in the Cadence Palladium flow — 6–12× speedup on multi-million-cell designs
- Production-ready primitives validated on industrial-scale benchmarks
Graph Neural Networks for Placement, Congestion & Floorplanning
Core focus: learning cell-, net-, and layout-level representations directly from the netlist to guide classical engines.
- Timing-driven placement: GNN-based initialization that warm-starts the analytical placer TODAES 2026
- Routing congestion prediction for the Cadence Palladium (Z4) emulator
- Data-driven floorplanning trained on the FloorSet dataset of real-world SoC layouts
An Agentic System for End-to-End VLSI Physical Design
Core focus: an LLM-driven agent that plans and executes the full floorplan-to-route flow under unified PPA objectives (Ph.D. dissertation).
- Agent over a real flow: orchestrates ML engines and commercial EDA tools across floorplanning, placement, legalization, routing
- Grounded in reliable primitives: invokes the TwinTree legalizer and GNN-guided engines
- Physically valid states: topological invariants and solver-based checking keep every action legal
Physical-Aware Redaction, Logic Locking & Secure Accelerators
Core focus: protecting hardware IP across the stack, and extending circuit-protection techniques to secure AI systems.
- eFPGA redaction: GNN-guided, physical-aware redaction as graph partitioning DATE 2026
- Logic locking: ObfusLock, DE2, and DNN logic-locking analysis
- Secure AI accelerators: LLA — logic-locked accelerators for generative models AAAI 2025
Rigorous Verification for Design Transformations
Core focus: automated equivalence checking for sequential, non-cycle-accurate transformations, plus formal reasoning about learned models.
- SE3: sequential equivalence checking with no cycle-accuracy or latch-mapping assumptions DAC 2023
- RE3: automatic discovery of refinement relations, applied to LLM-generated RTL DAC 2025
- Global robustness: certifying robustness of deep neural networks
Transferable ML Beyond Hardware
Core focus: applying ML expertise to real-world problems beyond hardware.
- Multimodal medical diagnosis: Bayesian networks + deep learning for skin-disease detection
- 19.3% accuracy improvement over pure deep learning ISBI 2023 · BIBM 2024
Research Vision
I believe physical design and machine learning are mutually empowering. ML gives classical engines better starting points and predictions; a legalizer with strong invariants gives ML a safe, physically valid space to explore. My goal is to unify these into an agentic design flow — one that drives floorplanning to routing under unified PPA objectives, invoking reliable primitives and commercial tools while staying provably legal.
Key insights:
- PPA-driven: every technique is judged by whether it moves power, performance, and area
- Physical-awareness matters: EDA quality depends heavily on physical-awareness in ML representations
- From primitives to agents: reliable engines (legalization, GNN placement) compose into an autonomous flow
This research is conducted at the NuLogiCS Research Group, Northwestern University, in collaboration with Cadence Design Systems and industry partners.