Physical-Aware eFPGA Redaction for Secure and Efficient Hardware IP Protection

Authors: Yunqi He, You Li, Ruofan Huang, Guannan Zhao, Hai Zhou

Venue: Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2026

eFPGA redaction protects hardware IP by mapping selected logic onto a reconfigurable fabric, but the choice of what to redact must respect physical-design constraints to remain efficient. This work presents a physical-aware eFPGA redaction flow that treats region selection as a graph-partitioning problem: GNN models over gate-level netlists and placement features guide constrained region selection with embedding-driven clustering under area and timing budgets. A multi-stage ML–EDA flow interleaves GNN-guided decisions with Yosys, OpenSTA, and OpenROAD, and closes the loop with OpenFPGA-based fabric generation, yielding an end-to-end pipeline for secure, verifiable design transformations that balances area, timing, and security under explicit budgets.