Portfolio item number 1
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Short description of portfolio item number 2 
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Applying ML expertise to solve real-world problems beyond hardware, demonstrating transferable machine learning techniques through multimodal medical diagnosis systems with significant accuracy improvements.
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Protecting hardware IP across the stack — physical-aware eFPGA redaction guided by GNNs, logic-locking schemes (ObfusLock, DE2), and extending circuit-protection techniques to secure AI accelerators (LLA).
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Rigorous, automated equivalence checking for sequential, non-cycle-accurate design transformations — SE3 and RE3 — plus formal reasoning about the robustness of learned models.
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Building physical-design methodology and GPU-accelerated flows that turn continuous placements into legal, high-quality layouts — a TwinTree-based quality-preserving legalizer and DREAMPlace-based acceleration validated on industrial-scale designs.
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Graph neural networks that learn directly from netlist and layout features — timing-aware placement initialization, routing-congestion prediction, and data-driven floorplanning trained on real-world SoC layouts.
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An LLM-driven agent that plans and executes the full physical-design flow — floorplanning, placement, legalization, and routing — invoking ML engines and commercial EDA tools under unified PPA objectives while staying on physically valid states.
Published in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023
This paper is about ObfusLock, a novel logic locking scheme that simultaneously achieves I/O attack resilience, structural attack resilience, locking efficiency and protection diversity.
Published in IEEE 20th International Symposium on Biomedical Imaging (ISBI), 2023
This paper is about an automatic skin disease diagnosis architecture that combines deep neural networks as nodes into Bayesian networks, which combines human knowledge with the perceptual results of deep learning tools.
Published in 60th ACM/IEEE Design Automation Conference (DAC), 2023
This paper is about SE3, an efficient sequential equivalence checker without assumption on cycle-accuracy, latch mapping, or I/O interface of the checked circuits.
Published in arXiv preprint arXiv:2405.20556, 2024
A method for certifying the global robustness of deep neural networks, providing guarantees that hold across the input space rather than only around individual samples.
Published in 61th ACM/IEEE Design Automation Conference (DAC), 2024
This paper demonstrates the vulnerability of HPNN-style logic locking schemes on deep neural networks by proposing a systematic I/O attack that combines algebraic and learning-based approaches to efficiently extract protected parameters.
Published in 27th Information Security Conference (ISC), 2024
This paper is about INCISE, a symbolic model checking algorithm that efficiently searches for secure configuration spaces, enabling system engineers to quickly verify configuration security, and successfully demonstrated its effectiveness on cellular network emergency call systems.
Published in 2024 IEEE International Conference on Bioinformatics and Biomedicine (BIBM), 2024
This paper proposes an extensible multimodal Bayesian network architecture that efficiently integrates deep neural networks with clinical metadata for skin disease diagnosis, achieving 19.3% accuracy improvement over baseline methods.
Published in 2025 Design, Automation & Test in Europe Conference (DATE), 2024
This paper introduces DE2, a novel SAT-based attacking algorithm that leverages high-level functional specifications for sequential logic decryption, featuring an automatic alignment mechanism and the LIM algorithm for enhanced logic locking analysis.
Published in 62nd ACM/IEEE Design Automation Conference (DAC), 2025
This paper presents a rigorous and efficient sequential equivalence checking algorithm for non-cycle-accurate designs that can automatically find concise and human-comprehensible refinement relations, with applications including regression verification and LLM-generated RTL design validation.
Published in AAAI Conference on Artificial Intelligence, 2025
LLA applies logic-locking techniques to hardware accelerators to protect the security and privacy of generative models, extending circuit IP-protection methods to modern AI systems.
Published in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2026
A physical-aware eFPGA redaction flow that uses GNN-guided region selection and OpenFPGA-based fabric generation to protect hardware IP while balancing area, timing, and security under explicit budgets.
Published in ACM Transactions on Design Automation of Electronic Systems (TODAES), 2026
Graph neural networks learn cell- and net-level embeddings from the netlist to produce timing-aware initial placements, warm-starting the analytical placer to cut placement iterations and improve post-placement timing.
Published in International Conference on Computer-Aided Design (ICCAD), 2026
A new legalization workflow that preserves the quality of analytical floorplanning: twin binary trees capture the relation between adjacent blocks and a differentiable model optimizes their coordinates, matching or surpassing commercial and open-source macro placers on the TILOS MacroPlacement benchmarks in post-route timing and wirelength.
Published:
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Undergraduate course, University 1, Department, 2014
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Workshop, University 1, Department, 2015
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